1. Field of the Invention
The present invention relates to the fabrication of self-aligned contacts on semiconductor devices, and more particularly to a method for making self-aligned source/drain contacts and a well insulated gate electrode using a non-conformal protecting layer.
2. Description of the Related Arts
Because the trend of semiconductor manufacturing towards highly integrated devises, the mis-patterning tolerance is becoming stricter. Recently, a self-aligned contact which partially overlays the source/drain and the gate electrode has been developed to increase the tolerance of mis-patterning and enhance the density of the integrated devises.
A conventional self-aligned contact is typically fabricated by the following procedures. Referring to FIG. 1A, a gate oxide layer 112, a gate electrode layer 114 and a first protecting layer 116 are successively formed over a semiconductor substrate 110. The gate oxide layer 112 is composed of silicon oxide and deposited by high temperature oxidation in an oxygen ambient. The gate electrode 114 is composed of doped polysilicon and deposited by chemical vapor deposition. The first protecting layer 116 is composed of silicon nitride and deposited by chemical vapor deposition. Then, a photolithographic technique and an anisotropical technique are used to pattern these layers.
A lightly doped region 120 is formed by ion implantation using the patterned first protecting layer 116 as the mask. Insulating sidewall spacers 122 are formed on the sidewalls of the gate oxide layer 112, the gate electrode layer 114, and the first protecting layer 116. The insulating sidewall spacers 122 are fabricated by depositing a silicon nitride layer over the substrate 110 and etching it back to the top of the first protecting layer 116. Preferably the sidewall spacers 122 are composed of silicon nitride and formed by, for example, chemical vapor deposition.
A highly doped region 124 is then formed in the substrate areas adjacent to the insulating sidewall spacers 122 by ion implantation using the first protecting layer 116 and the insulating sidewall spacers 122 as the mask.
A second protecting layer 126 is formed to conformally, blanket the first protecting layer 116, the insulating sidewall spacers 122 and the substrate 110. Conventionally, the second protecting layer 126 is a TEOS oxide layer formed by low-pressure chemical vapor deposition using tetra-ethyl-ortho-silicate (TEOS) as the reactant.
Referring to FIG. 1B, a interlayer insulating layer 128 is formed thereon to isolate the transistor and conducting layers which will be formed later and to offer a good planar surface for the following procedure. Preferably, the layer 128 is formed of doped silicon oxide such as borophosphosilicate glass (BPSG) by chemical vapor deposition.
Referring to FIG. 1C, the self-aligned contact 132 is formed. The result is achieved by using the photoresist film 130 as the mask and anisotropically etching the interlayer insulating layer 128 and the second protecting layer 126, usually formed of silicon oxide, until the heavily doped region 124 is exposed. Then, a conducting material 134 is implanted into the self-aligned contact 132 and contacts with the heavily doped region 124, as indicated in FIG. 1D.
Unfortunately, several problems result because the material of the second protecting layer 126, which is usually TEOS oxide, is similar to that of interlayer insulating layer 128, doped silicon oxide. The etching selectivity between TEOS oxide and doped silicon oxide is not high enough. When the interlayer insulating layer 128 is patterned in order to form the self-aligned contact 132, the second protecting layer 126 is easily removed at the same time and can't provide good protection for the gate electrode 114. Without the protection of the second protecting layer 126, it is unavoidable to etch away part of insulating sidewall spacers 122 (silicon nitride) and form a gap in the spacer 122 during the pattering steps. A new spacer 122a is formed and allows the direct contact between the conducting material 134 and the gate electrode 114 through the gap. This generates a short-circuit as indicated in FIG. 1E.
Furthermore, the first protecting layer 116 may be partially etched and another gap formed in the first protecting layer 116 because of the mis-patterning. The resultant is shown in FIG. 1F. Through the gap in the first protecting layer 116, the contacting material 134 may directly contact with the gate electrode 114. This also causes a short-circuit.